The present invention relates to a SRAM (static random access memory) in which in particular its cell size is made to be small and its high speed processing is made to be possible.
Description of the Related Art
FIG. 1 is a circuit diagram showing an equivalent circuit of a high resistance load type SRAM. In this high resistance load type SRAM, loads R1 and R2 are made of a resistive film such as polysilicon, therefore the number of transistors is small enough compared with a SRAM in which loads are composed of transistors. Moreover, this resistive film can be formed in multi-layer, therefore the area of memory cell can be reduced and this SRAM has an advantage to be high density. This type of SRAM is constituted of two driving MOS transistors (hereinafter referred to as driving transistor) Qd1 and Qd2, and two transferring MOS transistors (hereinafter referred to as transferring transistor) Qt1 and Qt2. These transistors are connected to the high resistance loads R1 and R2, and a VCC line being a first power supply and a GND line being a second power supply, and word lines WL1 and WL2, and bit lines BL1 and BL2. The processing of writing and reading information at a SRAM is well known widely, therefore this explanation is omitted.
FIG. 2 is a sectional view showing an example of the conventional SRAM. FIGS. 3A, 3B, 3C and 3D are plane views showing each layer of a cell of the conventional SRAM. Referring to FIGS. 2, 3A, 3B, 3C and 3D, the structure of the SRAM is explained. An element separating oxide film 202 is formed in a required pattern on a semiconductor substrate 201. A gate oxide film 203 is formed on the active area partitioned by this element separating oxide film 202. On this gate oxide film 203, a gate electrode 204 is formed using polysilicon made to be low resistance and polycide made of silicide. A part of this gate electrode 204 works as word lines WL1 and WL2. A N type impurity is implanted to the active area which is partitioned by the element separating oxide film 202 and is masked by the gate electrode 204, and a source/drain area 205 of the MOS transistor is formed. With mentioned above process, the first and second driving transistors Qd1 and Qd2, and the first and second transferring transistors Qt1 and Qt2 are formed with the gate electrode 204 and the source/drain area 205 (FIG. 3A).
Next, a first dielectric interlayer 206 is formed on the whole surface. As shown in FIG. 3B, after a contact hole 207 is opened at each source area of the driving transistor Qd1 and Qd2, a silicide layer is formed on the whole surface and this silicide layer is formed into a required pattern and a GND line 208 is formed. After a second dielectric interlayer 209 is formed on this, a contact hole 210 between the first dielectric interlayer 206 and the second dielectric interlayer 209 is opened. A high resistance polysilicon film is formed at the area including this contact hole 210 and is formed into a required pattern and high resistance loads 211 (R1 and R2) are formed. The contact hole 210 is formed as a shared contact hole. At a part of the polysilicon film which composes the high resistance load 211, as shown in FIG. 3C, a VCC line 212 is formed by implanting impurity selectively and lowering the resistance. A third dielectric interlayer 213 is formed on the whole surface. And a bit line contact hole 214 is opened, by penetrating from the first dielectric interlayer 206, the second dielectric interlayer 209 and the third dielectric interlayer 213, and reaches the source areas of the transferring transistors Qt1 and Qt2. An aluminum film is formed on the whole surface and is formed into a required pattern, as shown in FIG. 3D, bit lines 215 (BL1 and BL2) which make the bit line contact hole 214 bit line contact are formed. And a passivate dielectric interlayer 216 is formed on the whole surface and the SRAM is completed.
However, in this kind of SRAM, in order to increase the density of memory cells, the reduction of the area of the memory cell has been tried. As one of the methods to achieve this, the designing of the respective patterns of transistors, high resistance loads, and a first and a second power supply lines and the layout has been suitably implemented. The SRAM shown in FIG. 2 is one of the solutions. However, in this conventional SRAM, each conductive layer laminated on the semiconductor substrate is composed of the gate electrode 204, the VCC line 212 or the GND line 208, the high resistance load 211, and the bit line 215 from the bottom in sequence. Therefore, the shared contact hole 210, to which the drain area and gate electrode of the driving transistor, the source area of the transferring transistor and the high resistance load are connected together, is formed penetrating the first dielectric interlayer 206, the GND line 208 and the second dielectric interlayer 209.
As mentioned above, the shared contact hole 210 must be formed penetrating the GND line 208, therefore the depth of the shared contact hole 210 is liable to be deep. Therefore, at the case that the area of the shared contact hole 210 is made to be fine structure, the aspect ratio becomes large, the filling high resistance load material into the shared contact hole 210 becomes difficult and it becomes a factor to increase the shared contact resistance. Considering the mask position shift by the photo lithography technology at forming the shared contact hole 210 and the pattern position shift of the GND line 208 existing at the area where the shared contact hole 210 is penetrated, a required layout margin MG1 must be secured in order not to be shorted the shared contact hole 210 to the GND line 208. Therefore, because of that the area for the layout margin MG1 must be secured between the shared contact hole 210 and the GND line 208, this layout margin area becomes an obstacle at reducing the area of the memory cell.
Moreover, the bit line contact hole 214 is needed in order to connect the bit line 215 to the drain area of the transferring transistor formed on the semiconductor substrate. This bit line contact hole 214 is formed penetrating the high resistance load 211, the VCC line 212, the GND line 208 and the gate electrode 204. The layout margin of each layer for this bit line contact hole 214 must be also secured. Especially, the VCC line 212 is the polysilicon made to be low resistance and is difficult to be made low resistance compared with the metal material. Therefore, the area of the VCC line 212 is made to be as large as possible in the designing, and securing a layout margin MG2 between the bit line contact hole 214 and the VCC line 212 is needed. Consequently, it is difficult to reduce the cell length L2 shown in FIG. 2. At the bit line contact hole 214, as the same as the shared contact hole 210, the problem that the aspect ratio becomes large and the contact resistance increases occurs.
Furthermore, at the memory cell shown in FIG. 2, the GND line 208 is extended right under the bit line 215 being the uppermost layer, and the second dielectric interlayer 209 and the third dielectric interlayer 213 are positioned between the bit line 215 and the GND line 208. By this, the wiring capacity of the bit line 215 becomes large, it becomes an obstacle to realize the high speed writing and reading for the memory cell.
As this kind of SRAM, several Japanese patent applications are disclosed. For example, the Japanese Patent Application Laid-Open No. HEI 7-240477 discloses a SRAM using a high resistance load made of polysilicon. At this SRAM, a gate electrode is formed by a first layer polysilicon film, a word line is formed by a second layer polysilicon film, a high resistance load and a first power supply line are formed by a third layer polysilicon film, and a second power supply line and a bit line are formed by a first layer aluminum film. At this structure, a shared contact hole connecting the gate electrode and the high resistance load must be formed penetrating the second layer polysilicon film being the word line. Therefore, the aspect ratio becomes large and a margin for the second layer polysilicon film must be secured, and the occurrence of the mentioned above problems is not avoided.
The Japanese Patent Application Laid-Open No. HEI 8-274190 discloses a SRAM. At this SRAM, a gate electrode is formed by a first layer polysilicon film, a first and a second power supply lines are formed by a tungsten film, a high resistance load is formed by a SIPOS (semi insulated polysilicon), and a bit line is formed by an aluminum film. This SRAM have also the same problem as the Japanese Patent application Laid-Open No. HEI 7-240477. And the Japanese Patent Application Laid-Open No. HEI 8-241929 discloses the same kind of SRAM.